The disclosed subject matter relates generally to electronic devices having multiple power states and, more particularly, to a method and apparatus for transitioning devices between power states based on activity request frequency.
The ever increasing advances in silicon process technology and reduction of transistor geometry makes static power (leakage) a more significant contributor in the power budget of integrated circuit devices, such as processors (CPUs). To attempt to reduce power consumption, some devices have been equipped to enter one or more reduced power states. In a reduced power state, a reduced clock frequency and/or operating voltage may be employed for the device.
FIG. 1 is a diagram 100 illustrating conceptually a trade-off between transitioning into a reduced power state and state residency. The active state is designated as the C0 state, and a particular reduced power state is designated as Cn. The value of n may change depending on how deep the power state is (i.e., higher value of n reflects a deeper power state. The reduced power state may be broken down into three regions, Cn state entry (i.e., from the current power state to the reduced power state), Cn state residency, and Cn state exit (i.e., from the reduced power state to an exit power state, which may be different than the current power state), each consuming different amounts of energy. Energy consumed during entry and exit transitions is dependent on transition activity and the time spent for the transition. Although sharp transitions are illustrated in FIG. 1, the actual transitions are generally ramped transitions. As a general rule—the deeper the power state, the longer the transition time required and the more energy consumed getting to the state. A reduced power state Cn is considered an efficient state (i.e., recommended to be entered) only if its Cn residency is sufficiently long to make the overall power consumption getting into and out of the reduced power state and spent in the reduced power state lower than the power consumption in the original power state for the same duration.
FIG. 1 shows various power levels associated with the device, such as C0 active and idle powers, Cn entry, exit, and idle powers, and a zero power level. When comparing transitions to various available power states, it is useful to compare the transitional energy of a particular power state and the power saved during the Cn residence to the power that would have been consumed without the power state transition. As seen in FIG. 1, the energy consumed during the Cn entry region, En(entry), is the difference between the Cn entry power level and the C0 idle power level (i.e., which would have been consumed if the device were left idle in the C0 state) integrated over the Cn entry time. Similarly, the energy consumed during the Cn exit region, En(exit), is the difference between the Cn exit power level and the C0 idle power level integrated over the Cn entry time. The energy saved during the Cn residency region, En(Δ), is the difference between the C0 idle power and the Cn idle power integrated over the Cn residency time. Hence, En(entry) and En(exit) represent the energy cost of transitioning to the reduced power state, while En(Δ) represents the energy savings realized during the reduced power state residency.
Reduced power state Cn is considered an efficient state (i.e., recommended to be entered) only if its Cn state residency is sufficiently long to make the overall energy savings in the Cn state greater than the energy consumption during the power state transitions.En(Δ)>En(entry)+En(exit).
When comparing two candidate reduced power states, reduced power state Cn is more efficient that reduced power state Ck if:En(Δ)−En(entry)−En(exit)>Ek(Δ)−Ek(entry)−Ek(exit).
There is a cost to transitioning to a reduced power state defined by the entry and exit power consumption. The deeper the power state is, the longer it takes to transition in and out of it. Longer transition latency makes the state both less power efficient and introduces functional risk for workloads requiring well-bounded interrupt latency (e.g., playbacks, network workloads, Sysmark Benchmark, etc.) The problem of interrupt latency is generally addressed by design methods that seek to reduce exit latency (e.g., faster voltage and/or frequency ramp-up, faster restore of the processor state in cases where the processor loses its state in the reduced power state, etc.).
To lower overall power, if there is a power penalty associated with transitioning to a lower power state, the residency in the lower power state must be such that the power associated with the transition into and out of the state added to the power consumed in the lower power state must be lower than if no state transition had occurred.
Transitioning to lower power states may impose performance constraints on the system—for example, low power states may add to the time to service interrupts. The deeper the reduced power state, the longer it takes to transition back to the operational state. This extra latency may have a negative effect on performance of some video, audio or network applications that are very sensitive to long interrupt service latency. This sensitivity may be perceived as user-visible or user-audible real-time artifacts (i.e., lost frames, late audio stream, etc.) or may be manifested as an underperformance of the application. If this happens on a frequent basis the performance loss or real-time effects become more apparent, negatively impacting the user experience.
For microprocessors, currently known Advanced Configuration and Power Interface (ACPI) and ACPI-based low-power states have been employed to reduce dynamic power consumption and reduce CPU static power. ACPI is an open industry standard that defines common interfaces for hardware recognition, motherboard and device configuration, and power management. A widely recognized element of ACPI is power management—giving the Operating System (OS) control of power management, in contrast with prior models where power management control was mainly under the control of the Basic Input/Output System (BIOS), with limited intervention from the OS. In ACPI, BIOS provides the OS with methods for directly controlling the low-level details of the hardware, providing the OS with nearly complete control over the power saving schemes.
The ACPI standard specifies various groups of states, among them global states, device states, performance states, and processor states. For example, the ACPI standard defines four processor power states, C0-C3. C0 is the operating state. C1 (often referred to as Halt state) is a state in which the processor is not executing instructions, but can (essentially) instantaneously return to an executing state. C2 (often known as Stop-Clock state) is a state in which the processor stops clocks but maintains cache contents and all software-visible state data. Because cache contents are maintained in C2, the processor must still service coherency probes. C3 (often known as Sleep state) is a state in which the processor maintains cache contents and software state, but lowers voltage to a level sufficient to maintain the saved state. While the ACPI standard specifies 4 states (C0-C3), processors can have independently-defined hardware states beyond C3 representing progressively lower power states. Incremental improvements can be made by flushing cache contents so that the core no longer needs to participate in coherency probes (C5 state). The lowest power state is achieved when the processor cache contents and software context are saved and supply voltage is reduced to eliminate leakage. (C6 state).
It should be noted that the C6-state is not equivalent to system sleep state S3 where most of the system is powered down, and restoration to the C0-state requires an extended period of time, oftentimes in the range of many seconds. The C6-state can be applied to a single-core processor or to any core or group of cores in multi-core processors, while keeping other cores and system components (chipset, I/O, DRAM) in fully functional states. At the moment the OS indicates the need for allocating some task/process on a given CPU that is presently in the C6-state, that CPU is powered-up and becomes available for executing the requested task/process. Effectively managing a processor's transitioning in and out of the C6-state can lead to improved power management and result in reduced overall power consumption.
This section of this document is intended to introduce various aspects of the art that may be related to different aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the different aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.